Design and Implementation of an Efficient Instruction Set Simulator for an Embedded Multi-Core Architecture
Published in , 2011
This thesis develops the concepts required for efficient multi-core just-in-time dynamic binary translation and demonstrates its feasibility and high simulation performance through an implementation in the ARCSIM simulator platform.
Recommended citation: Volker Seeker. Design and Implementation of an Efficient Instruction Set Simulator for an Embedded Multi-Core Architecture. Diploma Thesis. Programmierung Eingebetteter Systeme, Technische Universität Berlin, 2011.